In standard silicon complementary metal oxide semiconductor (CMOS) technology, n-type field effect transistors use an As (or other donor) doped n-type polysilicon layer as a gate electrode that is deposited on top of a silicon dioxide or silicon oxynitride gate dielectric layer. The gate voltage is applied through this polysilicon layer to create an inversion channel in the semiconductor substrate underneath the gate dielectric layer.
In future technology, silicon dioxide or silicon oxynitride dielectrics will be replaced with a gate material that has a higher dielectric constant. These materials are known as “high-k” materials with the term “high-k” denoting an insulating material whose dielectric constant is greater than 4.0, preferably greater than about 7.0. The dielectric constants mentioned herein are relative to a vacuum unless otherwise specified. Of the various possibilities, hafnium oxide, hafnium silicate, or hafnium silicon oxynitride may be the most suitable replacement candidates for conventional gate dielectrics due to their excellent thermal stability at high temperatures.
Silicon metal oxide semiconductor field effect transistors (MOSFETs) fabricated with a hafnium-based dielectric as the gate dielectric suffer from a non-ideal threshold voltage when n-MOSFETs are fabricated. This is a general problem, and in particular, when the MOSFET consists of HfO2 as the dielectric and TiN/polySi as the gate stack, the threshold voltage is in the 0.05 to 0.3 V range typically after standard thermal treatments. Ideally, the threshold voltage should be around −0.2 to −0.05 V or so.
U.S. patent application Ser. No. 11/118,521 filed Apr. 29, 2005 and entitled “Stabilization of Flatband Voltages and Threshold Voltages in Hafnium Oxide Based Silicon Transistors for CMOS” provides a solution to the above problem by incorporating a rare earth metal (or rare earth-like)-containing layer into the gate stack. In particular, the '521 application solves the above problem by disposing a rare earth metal (or rare earth like)-containing material on top of, or within a high-k gate dielectric. The presence of the rare earth metal (or rare earth-like)-containing material in the high-k gate stack stabilizes the flatband voltage and threshold voltage of the Si-containing conductor.
Despite overcoming the above mentioned problems with respect to flatband voltage and threshold voltage stabilization, the patterning of the high-k gate dielectric capped with a rare earth metal (or rare earth-like)-containing layer by lithography and etching, particularly wet etching, allows for a very low post-patterning remnant of rare earth metal or rare earth like-containing element (on the order of about 10 atoms/cm2 or greater) on the surface of the semiconductor substrate that adjoins the patterned gate stack.
The presence of the rare earth metal or rare earth like-containing element on the surface of the semiconductor substrate is problematic in that it results in metal gate etching and integration challenges.
For example, the prior art etching step used in patterning such gate stacks typically utilizes a wet etchant, which inherently undercuts the high-k gate dielectric due to the anisotropic nature of wet etching. That is, conventional wet etching of a gate stack including a high-k gate dielectric typically damages the high-k gate dielectric. In some instances, the prior art wet etching process damages the integrity of the gate conductor as well. Also, prior art etching of gate stacks including a high-k gate dielectric and a rare earth metal (or rare earth-like)-containing capping layer may result in recessing of the semiconductor substrate which lies at the footprint of the now patterned gate stack.
In addition to the above, the remnant of rare earth metal or rare earth-like-containing element that remains on the surface of the semiconductor substrate can negatively impact the ion implantation of source/drain extension and diffusion regions into the substrate.
In view of the above, there is a need for providing a new and improved method for patterning gate stacks including a high-k gate dielectric and a rare earth metal (or rare earth like)-containing layer which reduces the amount of remnant rare earth metal or rare earth like-containing element on the surface of a semiconductor substrate to levels that are acceptable in current complementary metal oxide semiconductor (CMOS) fabrication.